This invention relates generally to semiconductor wafer fabrication and more importantly to a method and apparatus for determining photoresist pattern linearity.
The process of photolithography has long been used in the semiconductor industry to produce integrated circuits. A circuit pattern is printed onto an actual semiconductor wafer using one of several methods of printing including projection printing. The production of integrated circuits involves having the designed pattern on the mask transfer into a photoresist image on the wafer as designed. Complete linearity results when the designed pattern transfers to the wafer exactly as designed for dimensions starting as low as 0.1 xcexcm up to several hundred micrometers. However, real world processes will result in some deviations in the transfer of the pattern. One deviation that occurs is a shift between the desired dimensions in design and the actual dimensions of a given feature or features in photoresist. For example, a design pattern may consist of lines whose widths may deviate from the desired dimensions when the pattern is transferred to the wafer. If the line width deviations are known for line widths between 0.1 xcexcm and 300 xcexcm, the design data can be corrected in order to print photoresist lines exactly to the designed target dimension. Therefore, the knowledge of photoresist linearity is important for the functionality of the integrated circuits.
One approach for determining pattern linearity is to view a cross section of a photoresist line on a wafer through a scanning electron microscope (SEM). A wafer is cut and the features of the wafer on the pattern are magnified and viewed to determine the linearity of the pattern edge. However, this approach requires destroying the wafer and is very expensive, time consuming, and may lead to inconclusive results especially for dimensions larger than 1-2 xcexcm because the required measurement accuracy (in the order of 0.01 xcexcm) is not achieved for structures greater than about 2 xcexcm in a SEM. This is so because larger critical dimensions are harder to view due to the low magnification, which is necessary to capture the whole structure. This results in larger errors in measurements.
Another approach for determining pattern linearity involves viewing the wafer from the top down through a scanning electron microscope. This approach does not destroy the wafer because the wafer is not cut or manipulated in any destructive manner. However, the approach has limited use. Generally, linearity of dimensions in the order of below 1 micron up to 1 or 1xc2xd xcexcm can be determined with accuracy. However, the determination of larger dimensions is subject to greater inaccuracy because of the SEM accuracy limitation discussed above.
Thus, what is needed is a method to determine linearity which is less costly and time consuming than the cross-section approach and which is more accurate across a wide range of critical dimensions
These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by preferred embodiments of the present invention which measures the linearity of a pattern printed on a semiconductor wafer having a photoresist layer into which the pattern, having a plurality of pattern feature, is transferred and having a plurality of layers located beneath the photoresist layer. In one preferred embodiment of the present invention, the method comprises determining an expected pattern edge for each of the plurality of pattern features from a design criteria, formulating measuring patterns for each of the plurality of pattern features, magnifying the semiconductor wafer, analyzing the magnified semiconductor wafer in a top down view, measuring the dimensions of each of the plurality of pattern features using the measuring patterns, and determining the linearity of the pattern utilizing the dimensions of each of the plurality of pattern features.
One of the advantages of a preferred embodiment of the present invention is that the semiconductor wafer is not destroyed during the test for linearity because the wafer is not cut or manipulated in a manner that would result in the wafer being unusable as a finished product.
Another advantage of a preferred embodiment of the present invention is that the method of the present invention is more cost effective than the conventional cross section approach because the wafer is not destroyed resulting in scrap materials, nor is money spent on the process of cutting the wafer.
Yet another advantage of a preferred embodiment of the present invention is that the measuring process is more time efficient because the wafer can be viewed in tact under the top-down scanning electron microscope.
Furthermore, a preferred embodiment of the present invention has the advantage of higher accuracy because the edge location of the photoresist lines can be more easily discerned.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.